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Altera_Forum
Honored Contributor
Honored ContributorLatches in frequecny divider using fsm implementation
I am new to verilog and HDL. I want to implement a N-frequency divider, which count clock ticks (pos and neg) and start the counting mechanism from the first rising edge of the input clk. In a...
Altera_ForumHonored Contributor
Honored ContributorOK, but as you said previously
FPGAs doesn't support both falling and rising edges of signal. is that means every verilog module targeted for FPGA can't have sensitivity list without stating the edge of the signal? Thanks
