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Honored Contributor
Honored ContributorLatches in frequecny divider using fsm implementation
I am new to verilog and HDL. I want to implement a N-frequency divider, which count clock ticks (pos and neg) and start the counting mechanism from the first rising edge of the input clk. In a...
Altera_ForumHonored Contributor
Honored ContributorRegisters in an FPGA only have a single clock input, hence one register can only use a single clock, either a rising or falling edge.
You may be able to separate the counters, but they will be in separate clock domains and combining them will not be so trivial. Much easier just to use a 2x clock.
