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Altera_Forum
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13 years ago

Latch inference is Quartus bug or specified VHDL behaviour?

Hello, does anybody know, why Quartus infers latches for the below combinational function if we use an initial value expression for the variable definition of mirrored_data? I looks like a Quar...
Altera_Forum's avatar
Altera_Forum
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13 years ago

ModelSim RTL simulation functions OK. I don't have a 'dataflow' licence (ASE) so I can't see the RTL it generates.

I think it is safe to say it is a Quartus bug, but wouldn't bother to file an SR as the Altera gang will tell us to work-around it the way Kaz proposes. Which is not a problem to me, I never initialize a variable at the declaration, not even in C or C++ programs. I always initialise a variable just prior to the first use, to my idea it better documents what's going on.

Setting the SIZE to 2, with the initialiser enabled, doesn't crash in 12.1 (32 bit)