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initialisation means that the value is applied once only at start only(first sample).
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VHDL spec tells the opposite "the initial value of the variable is determined by that expression each time the variable declaration is elaborated".
Another strange point is, that latches are inferred even if the initial value expression is overwritten by a succeeding unconditional assignment. In other words, even if the initial value expression would be treated different, the sequential elaboration of VHDL statements seems to be invalidated.
I have no problem to accept a - as it appears to me yet - minor Quartus bug that can be easily avoided. But we shouldn't read an expectable or even required behaviour into it, if it isn't.
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