Latch inference is Quartus bug or specified VHDL behaviour?

Or put it this way. When initial value is constant then it translates to wires connected to ground or source, no latching needed. If it is variable and hence unknown then the logic has look for it and keep it on wires and this implies latching. I would rather avoid it.

Edit: Note also that initialising a variable(or signal) is conceptually different from appling a default value in a running process.

Default value implies running assignment that can have conditional update in subsequent code.

initialisation means that the value is applied once only at start only(first sample).