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I'm no aware of a limitation.
In fact there's a simple solution for the problem, use an explicite assignment instead of the initial value expression, as in my code example. Personally, I'm preferring this style anyway.
The initial value expression should give the same result, but it doesn't.
The VHDL spec tells in chapter 4.3.1.3 Variable declarations:
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Ok that implies you can but I don't see how the function call will synthesize to a fixed initial value if data is a variable. In other words I presume the synthesized logic must latch the intial value to know it then apply it.
Adding register to y just masks the issue.
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