Large interconnect delays on clock

Stepping back, it's not common to do a functional "post-synthesis" simulation. The most common approach is to do a functional simulation with the RTL and static timing analysis to make sure the timing is right. If done correctly, that should be enough. On top of that users often do post-fit timing simulations. They're slow, and they really aren't as robust at catching things as most users think, but it used to be a common practice(especially for ASICs, where the cost of a mistake was too high and there wasn't any way to just run the hardware and see if anything went wrong.)

Anyway, you state you're doing a functional simulation(which implies no timing) but are including the .sdf(which is the timing file). So I'm a little confused. Just a suggestion, but you might want to just do a post-fit timing simulation on the full design(or not at all). Naturally, if you're just simulating a sub-component, then the delays outside of that sub-component(like clock delays) may not be realistic unless you go through the hurdles to make them realistic(like adding the PLL).