Large interconnect delays on clock

Hello,

For now, I instantiated a PLL (but that is not supposedly included in the subdesign) just to get the correct resource assignment of the clocks and get a more realistic delay.

This works, for now, but I am very interested in knowing how to do a functional simulation using the postsynthesis netlist if the delays on the clock signals of the said netlist are not "realistic" because it was compiled bottom-up.

regards,

edzel