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Altera_Forum
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16 years ago

Large interconnect delays on clock

Hello, I'm trying to do a test implementation of a design in StratixIII using Quartus. Since this module is only a part of a bigger project, I have set it as a partition and locked its location...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You can check that nothing funny is going on by doing a list paths in timequest and selecting the 'full path' option. This will show the breakdown of the clock network delay, so you can check if it is being routed how you expect.