Large interconnect delays on clock

No large-fanout net could have a delay of 0.3ns. It depends on device and speed grade, but a 3ns global delay sounds about right(some are larger, some are smaller). My guess is that in the full design it is driven by a PLL, so you still have your 3ns delay, but the PLL also compensates for that by shifting back approximately 3ns. In your sub-design you just have the global delay.

With the exception of I/O interfaces, this shouldn't matter much, since any clock transfers in that domain will have both the source and destination clocks delayed by ~3ns, so the net sum is that they cancel each other out.