Large delay through IO_OBUF

Hey Kaz,

I don't believe that is true in this case as this is data that is launched by the ADC using SCK and latched on the FPGA using my internal 50 MHz clock.

FYI the constraints are as follows:

# system clocks

create_clock -period 10.000 -name CLK_100MHZ [get_ports {CLK_100MHZ}]

create_clock -period 20.000 -name CLK_50MHZ [get_ports {CLK_2}]

# serial adc source sync external clocks (50MHz)

create_generated_clock -name CH4_AD_SCK -source [get_ports {clk_2}] [get_ports {CH4_AD_SCK}]

# *** slow serial ADC delays ***

set ssadc_in_min -3

set ssadc_in_max 10

set_input_delay -clock CH4_AD_SCK -min $ssadc_in_min -clock_fall [get_ports {CH4_AD_SDI}]

set_input_delay -clock CH4_AD_SCK -max $ssadc_in_max -clock_fall [get_ports {CH4_AD_SDI}]

set_output_delay -clock CH4_AD_SCK -min -1.000 [get_ports {CH4_AD_CNV}]

set_output_delay -clock CH4_AD_SCK -max 1.000 [get_ports {CH4_AD_CNV}]

I'm pretty sure my constraints are right, my main concern here is why the clock delay through the IO buf is so high, does anyone have any ideas how else to route the clock to get around this?

Thanks!

Jason