Large delay through IO_OBUF

The source latency of 10ns on launch and 30ns on latch are because this is a falling edge launch and falling edge latch with a 20 ns clock. No set_latency constraints were added to modify this, it was determined by timequest and as far as I can tell is correct.

You are right, there is a large external delay as well, I don't have a choice here, this ADC happens to have a ridiculously large setup delay, no getting around this as I can tell.

What I am primary curious about is why there is such a large delay on what seems to be to be a simple clock path. I was hoping there was some option in the compiler that I could tweak to fix this. I have a feeling this has something to do with the fact that I am routing a global clock to an output pad without going through a PLL. I know from my experience with the evils of ripple counters that you incur huge delays when you try to route a global clock through regular logic, for example a counter or an inverter.

At first, I had an inverter between the internal clock and the SPI output clock. When I saw the huge clock delay I figured it was being caused by the inverter, but when the delay persisted even after I removed the inverter I was perplexed. It seems to me that there has got to be a quicker way to get a global clock off the chip.

Jason