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Jun-Yan-Wu's avatar
Jun-Yan-Wu
Icon for New Contributor rankNew Contributor
5 years ago
Solved

It produced no waveform output(xx) of the state machine using d flip-flop

I was trying to stimulate the state machine with d flip-flop. There wasn’t any error while compiling. But whatever the input value I set, the University Program VWF doesn’t produced any waveform outpu...
  • SyafieqS's avatar
    SyafieqS
    5 years ago

    Hi Jun,


    I would suggest you to view you RTL netlist and see the logic if they are designed as intended and the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer and State Machine Viewer to check your design visually before simulation. Tool --> Netlist Viewer --> RTL viewer/state machine viewer.


    Analyzing Designs with Quartus II Netlist Viewers

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51013.pdf


    Thanks,

    Regards


SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Jun,


I would suggest you to view you RTL netlist and see the logic if they are designed as intended and the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer and State Machine Viewer to check your design visually before simulation. Tool --> Netlist Viewer --> RTL viewer/state machine viewer.


Analyzing Designs with Quartus II Netlist Viewers

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51013.pdf


Thanks,

Regards