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Altera_Forum
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11 years ago

Issues reading testvector file using Modelsim

Hello everyone! I am trying to run a testvector from my code using SystemVerilog but I'm having an issue reading the file. My code is as follows: logic testvectors; $readmemb("C:\Users...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You might try changing the \ to \\ or /. \ is an escape character in a Verilog string.