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Altera_Forum
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11 years ago

issues in running CycV_SoC with DDR3 RAM on Dev_Kit

Hello, I am in an internship and my task is to perform a DDR3-SDRAM memory test on the "Cyclone V SoC Development Kit" with the Cycone V SX 5SCXFC6.. FPGA. ( To see what the difficulties are ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Socrates,

I fixed the issue with help from the customer support :)

Currently I am running some memory tests and will post my solution soon.

First of all the preconfiguration of the Micron RAM is the problem for the pin_assignment warnings, cause the supply voltage is "1.5V DDR3" and some memory initialization options have to be changed. Furthermore one should copy the "Memory Timing" + "Board Settings" from a reference design of the corresponding Evaluation Kit.

Next problem is with the reset sequence and a possible deadlock when you auto generate a reset network.

... there are some more points to be considered to fix the cirtical warnings concerning ddr timings, but I will show my results soon.

Which board are you using?

I hope this could help you a bit.

Kind regards.