New ContributorIssues Building Intel Nios V/g core
I have just installed Quartus Pro 24.2, but I am having issues building designs containing Nios V/g.
I downloaded the Arria 10 Nios V/g Design Example, but when I try to build it I get an Error during the Analysis and Synthesis step saying this:
Verilog HDL or VHDL error: cannot open Verilog file 'ip/sys/cpu/intel_niosv_g_unit_220/synth/niosv_opcode_def.sv'
This error is repeated for most of the other files within that folder, specifically it's all the binary/encrypted files where I can't view the source code, but this error doesn't occur for the files which can be viewed in a text editor.
I also downloaded the Arria 10 Nios V/m Design Example, and that builds without issues, so my problem seems to just relate to the Nios V/g. Does anyone know what could be causing this and what can be done to fix it?
Many Thanks,
Samuel
I thought it might be a license issue but I was confused as I have a valid license which I've used to build Nios V/g in Quartus Standard, however I've realised the Flexlm License Daemon we were using was out of date, and updating it to a newer version has resolved my issue.
I'm surprised Quartus doesn't give a warning about this, or even that Quartus opens if I was using an unsupported version, but at least I've fixed it now.
Thank you for your reply,
Samuel
