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As output of FIFO is driving something, I am not supposed to have unknown even when clear is active.
So I am expecting output of FIFO to be zero when clear is active.
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Then you will need to change your expectations to match what the component actually does. Possibly, you have the FIFO configured to output data prior to being read in which case, since nothing has been put in yet, unknowns are the output. Or maybe the clock isn't running.
In any case, the data output of any FIFO is only valid under certain conditions which depend on how the FIFO is configured to provide output data. Since you have downstream stuff that uses the data but does not factor in the data valid conditions, then you have a design issue to fix. That issue will not have anything to do with what the data outputs of the FIFO do when they are being reset.
Kevin Jennings
Honored Contributor
