Issue with Quartus Prime PRO for Stratix 10 when using a string type in a VHDL project.

Something has cut the code, so here it is again: ########################################################### library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity e1 is port( data : out std_logic_vector(3 downto 0); clk : in std_logic ); end e1; architecture arch1 of e1 is component e2 is port( data : out std_logic_vector(3 downto 0); clk : in std_logic; str_1 : inout string(1 to 4); vec_1 : inout std_logic_vector(31 downto 0) ); end component; shared variable str_1 : string(1 to 4); shared variable vec_1 : std_logic_vector(31 downto 0); shared variable s1, s2 : std_logic; begin instance_1 : e2 PORT MAP ( data => data, clk => clk, str_1 => str_1, vec_1 => vec_1 ); process begin wait until clk'EVENT and clk='1'; s1 := not s2; end process; process begin wait until clk'EVENT and clk='1'; if s2/=s1 then s2:=s1; str_1:="ABCD"; end if; vec_1(7 downto 0):= conv_std_logic_vector(character'pos(str_1(1)),8); end process; end arch1; library IEEE; use IEEE.STD_LOGIC_1164.all; entity e2 is port( data : out std_logic_vector(3 downto 0); clk : in std_logic; str_1: inout string(1 to 4); vec_1: inout std_logic_vector(31 downto 0) ); end e2 ; architecture arch1 of e2 is begin process variable clk2: std_logic; begin wait until clk'EVENT and clk='1'; data<=vec_1(3 downto 0); clk2:= not clk2; end process; end arch1; ########################################################### Best Regards, (jd)