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jrrguzman's avatar
jrrguzman
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Solved

Issue when manually instantiating clock buffers in Arria 10

Hi, I'm using a signal which is used in the design as logic and as clock (at separate locations). If I just run the design flow, Quartus (Prime Standard 17.0) is able to instantiate a clock buffer ...
  • jrrguzman's avatar
    jrrguzman
    7 years ago

    Hi all,

    I figured out the issue: The signal that I'm trying to buffer comes from a LVDS input and I do not instantiate the differential input buffer manually. At this point if I run the fitter-placement, it seems the clock buffer is placed before the inferred differential input buffer and it makes the fitter fail miserably because it can't find the signal, although synthesis has already inferred the LVDS input buffer. (@GNg​ Maybe something you should consider fixing for next Quartus releases).

    To work-around that, I had to manually instantiate the differential input buffer ussing the ALTERA primitive: ALT_INBUF_DIFF. With that in place Quartus does not complain and gets me a clean implementation.

    Cheers

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

How are you instantiating and connecting the clock control block to the rest of your design? Is it fed directly by an external clock or an internal signal in your design? If you show the code that may help. There must be some conflict. Can you also post the error messages the Fitter is giving you?

#iwork4intel