Issue when converting between multiple data types

Edit1: In VHDL no object can have a dynamic size.

Edit2 and 3: This is what I tried yesterday before giving you the hint. It looks a bit like your code, and generates a big RTL diagram and use quite some LCs

process( source , destination , msbd , lsb )
            variable si : natural ;
        begin
            output <= (others => '0') ;
            si := 0 ;
            for i in 0 to 31 loop 
            
                if ( i < to_integer( unsigned( lsb )) ) then
                    output(i) <= destination(i) ;
                elsif( i < (31 - to_integer( unsigned( msbd ))) ) then
                    output(i) <= source(si) ;
                    si := si + 1 ;
                else
                    output(i) <= destination(i) ;
                end if ;
                
            end loop;
        end process ;

I didn't restrict si's range, but that doesn'y change anything, neither in the RTL-diagram, nor in the amount of LCs (edit)

I didn't spot the '31 to 0' error, as Daixiwen did.

Another way to do the same:

It assumes you have a barrelshift component (look in Pedroni's Circuit Design with VHDL' page 187 ff.). The other operators are standard. Except the reverse function, which is is easy to write with a loop. The RTL diagram will be small and understandable, and it will use a lot less LCs.