New Contributor
New ContributorInfo (12128): Elaborating entity "plusarg_reader" for hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error (10174): Verilog HDL Unsupported Feature error at plusarg_reader.v(22): system function "$value$plusargs" is not supported for synthesis File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v Line: 22
Error (12152): Can't elaborate user hierarchy "ExampleRocketSystem:ExampleRocketSystem|SystemBus:subsystem_sbus|TLXbar:system_bus_xbar|TLMonitor:monitor|plusarg_reader:plusarg_reader" File: /home/arun/.local/lib/python3.10/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v Line: 635
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 329 warnings
Error: Peak virtual memory: 852 megabytes
Error: Processing ended: Wed Oct 11 22:46:26 2023
Error: Elapsed time: 00:00:33
Error: Total CPU time (on all processors): 00:00:49
Traceback (most recent call last):
File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 90, in <module>
main()
File "/home/arun/litex-boards/litex_boards/targets/terasic_de2_115.py", line 83, in main
builder.build(**parser.toolchain_argdict)
File "/home/arun/litex/litex/soc/integration/builder.py", line 367, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
File "/home/arun/litex/litex/soc/integration/soc.py", line 1332, in build
return self.platform.build(self, *args, **kwargs)
File "/home/arun/litex/litex/build/altera/platform.py", line 45, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/arun/litex/litex/build/generic_toolchain.py", line 123, in build
self.run_script(script)
File "/home/arun/litex/litex/build/altera/quartus.py", line 216, in run_script
raise OSError("Error occured during Quartus's script execution.")
OSError: Error occured during Quartus's script execution.
The verilog file is located at https://github.com/litex-hub/pythondata-cpu-rocket/blob/master/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v
Frequent ContributorOk, so here is what I see in the core of that verilog module:
`ifdef SYNTHESIS assign out = DEFAULT; `else reg [WIDTH-1:0] myplus; assign out = myplus; initial begin if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT; end `endif
and the error:
Error (10174): Verilog HDL Unsupported Feature error at plusarg_reader.v(22): system function "$value$plusargs" is not supported
which means that the compile variable SYNTHESIS is not set, so the code with the system task $value$plusargs() is being
fed into Quartus to compile. System tasks are in general not synthesizable constructs, so it throws the error, as expected.
You need to define SYNTHESIS to select the synthesizable code vs simulation code.
