Forum Discussion
Occasional ContributorIs waitrequestAllowance suported for Altera EMIF external mem interface?
" waitrequest will usually only be ...". There is no usually in RTL. There is always. So waitrequest may be asserted DURING the burst. This means everything connected to waitrequest must be combinatorial, and can't be pipelined.
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Super Contributorwaitrequest back to your user logic is handled by a combination of the signal coming from the agent (the EMIF IP) and the interconnect (usually for arbitration purposes but any time the agent can't currently accept a command).
If you initiate a burst and then waitrequest to your user logic goes high, that means your logic (host) gets access to the agent until the burst completes. As the Avalon spec shows (figure 14 and 15 in the latest version of the doc), for a burst, waitrequest will usually only be asserted at the beginning of the burst or whenever the interconnect (or agent) requires the host to continue asserting the control signals for some reason (typically arbitration).
I think this is why Adzim suggested using bursts, since waitrequest isn't held high throughout them.
Occasional Contributor" waitrequest will usually only be ...". There is no usually in RTL. There is always. So waitrequest may be asserted DURING the burst. This means everything connected to waitrequest must be combinatorial, and can't be pipelined.
Thanks for the help. You may close this ticket.
