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Altera_Forum
Honored Contributor
Honored ContributorIs this a bug?
While using the left-to-right stream operator in Modelsim Altera Strater Edition 10.1e with the following code:
module stream_bug();
bit stream='{32{1'b0}};
initial begin
$monitor("@%0d...
Altera_ForumHonored Contributor
Honored ContributorThere are no longer any simulator dependent sizes in Verilog or SystemVerilog. All numeric literals have an explicit or implicit size.
A numeric literal without an explicit size will be the larger of either: 32 bits or the number of bits needed to express the literal. See http://www.eda.org/svdb/view.php?id=1107
