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Altera_Forum's avatar
Altera_Forum
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12 years ago

Is there any timing constraint with asynchronous I/Os?

This might be a silly question. But I would appreciate your answer. A typical situation is either an UART input or UART output. For input, I use a counter running at system clock to sample the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes it is correct. And for your input, just remember to use several registers in series before sampling the signal to avoid metastability issues.