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HTong1's avatar
HTong1
Icon for New Contributor rankNew Contributor
6 years ago

Is there a way to easily show the constrained or derived clock frequencies?

The Quartus FMAX only shows frequencies of clocks the compiled design can run up to but does not show what the clock frequencies are constrained in the .sdc file or derived from PLL. While such info ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

If any path in a clock domain is failing timing based on the design and your .sdc, the clock will show up as red when you run a summary report.

You can run Report Clocks directly from the Tasks window; no need for any extra buttons.

#iwork4intel