Forum Discussion
HTong1
New Contributor
New ContributorIs there a way to easily show the constrained or derived clock frequencies?
The Quartus FMAX only shows frequencies of clocks the compiled design can run up to but does not show what the clock frequencies are constrained in the .sdc file or derived from PLL. While such info ...
sstrell
Super Contributor
Super ContributorIn the timing analyzer, generate a clock report (report_clocks). That shows a summary of all the clocks in your design.
In case you're not familiar with the tool, check out these trainings:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1116.html
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1117.html
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