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Altera_Forum
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8 years ago

Is there a pragma to prevent loop pipeline?

Hi, Is there a pragma in altera opencl which can prevent a loop being pipelined? I have some outer loop which do not have to be pipelined but inferred to be pipelined which (I assume) caused so...
Altera_Forum's avatar
Altera_Forum
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8 years ago

I am afraid there is no such option. Performance-wise, you wouldn't want to do this either. Pipelining outer loops will use excessive area only if the II is larger than one, forcing the compiler to increase the depth of the buffer to allow correct pipelining. If the II is one, the area overhead will be minimal, and the performance improvement will be substantial.