Is there a Bug about the Quartus II?

Hi!

I want to learn timing simulation with the Modelsim,but I meet a strange problem.I write a counter with the VHDL that can pass the RTL simulation but cann't pass the Gate level simulation.the Modelsim always notes that Errors occured in reading and resolving instances from compiled SDF file(s).

So I write the same function counter with the Verilog that can pass the RTL simulation and Gate level simulation,it's so amazing.

please help me?

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity FX is
port(clk:in std_logic;
     reset:in std_logic;
     dataout:out std_logic_vector(3 downto 0)
     );
end FX;
architecture behave of FX is
signal mid:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(reset='1')then
 mid<=(others=>'0');
elsif(clk'event and clk='1')then
 mid<=mid+1;
end if;
end process;
dataout<=mid;
end behave;

Verilog Code:

module FX(clk,reset,data_out);
input clk;
input reset;
output data_out;
reg middle;
assign data_out=middle;
always@(posedge clk or posedge reset)
begin
 if(reset==1'b1)
  begin
   middle<=4'b0;
  end
 else
  begin
   middle<=middle+1;
  end
end
endmodule
 

VHDL Testbench:

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
ENTITY FX_vhd_tst IS
END FX_vhd_tst;
ARCHITECTURE FX_arch OF FX_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL clk : STD_LOGIC;
SIGNAL dataout : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL reset : STD_LOGIC;
COMPONENT FX
 PORT (
 clk : IN STD_LOGIC;
 dataout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
 reset : IN STD_LOGIC
 );
END COMPONENT;
BEGIN
 i1 : FX
 PORT MAP (
-- list connections between master ports and signals
 clk => clk,
 dataout => dataout,
 reset => reset
 );
init : PROCESS                                               
BEGIN                                                        
 clk<='0';
 wait for 10 ns;
 clk<='1';
 wait for 10 ns;
END PROCESS init;
always : PROCESS                                                                                  
BEGIN                                                         
 reset<='0';
 wait for 100 ns;
 reset<='1';
 wait for 60 ns;
 reset<='0';
WAIT;                                                        
END PROCESS always;                                          
END FX_arch;

Verilog Testbench:

`timescale 1 ns/ 1 ns
module FX_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg reset;
// wires                                               
wire   data_out;
// assign statements (if any)                          
FX i1 (
// port map - connection between master ports and signals/registers   
 .clk(clk),
 .data_out(data_out),
 .reset(reset)
);
initial                                                
begin                                                  
 
clk=1'b0;
forever# 10 clk=~clk;
 
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
reset=0;
@(negedge clk);
reset=1;# 100;
@(posedge clk);
reset=0;# 10000;
 
end                                                    
endmodule