Is RTL Simulation the same as Functional Simulation

From Altera:

The RTL simulation is just the functional simulation of RTL codes.The RTL simulation is using the VHDL, Verilog HDL or system Verilog design source codes files.

The gate level timing simulation allows you to simulate your design with post-fit timing information. The gate level timing simulation require quartus II generated post-fit timing output netlist file (vho/vo) file and standard delay output file (sdo). The gate level timing simulation is to ensure that the FPGA device’s functionality is correct and meets the entire timing requirement after fitter (place & route flow) in Quartus II software. But, the gate level timing simulation of entire design can be very slow and usually should be avoided. Thus, the gate level timing simulation is not supported for Arria V, Cyclone V, or Stratix V devices. Thus, you are not able to run gate level timing simulation from Quartus II software.

Check page 1-2 of the following link for this information:

http://www.altera.com/literature/hb/qts/qts_qii53025.pdf

For timing check, you can use TimeQuest Static timing analysis tool for 28 nm devices.

If you enable the setting "Generate netlist for functional simulation only" and then click the Gate Level Simulation button, it will run ModelSim and then run a gate level functional simulation only. The gate level functional simulation uses post-synthesis (generated after analysis & synthesis) or post-fit functional netlist file (vho/vo generated after fitter) only to run simulation. The SDO output file is NOT generated by Quartus II if you enable “Generate netlist for functional simulation only” option. The SDO file is the file that contain timing delay information that allow you to perform back-annotation for simulation with VHDL simulators that use simulation libraries that are compliant with VITAL version 2.2b and version 3.0 (VITAL 95); back-annotation for simulation in Verilog HDL simulators and ect. Thus, the gate level functional simulation is to check the FPGA device’s functionality is correct after analysis & synthesis or fitter (place & route flow).

In general, the gate level simulation is run after RTL code is synthesized into a gate-level netlist. Since the gate level simulation of an entire design is using netlist file that contain the standard cells, it is expected to be slower than RTL simulation.

I am afraid it is really hard to tell user when to choose to do a gate level Functional Simulation rather than an RLT Simulation. As per my understanding, fewer FPGA designer going gate-level simulation since it takes long time to run gate level functional/timing simulation. Normally, the gate level simulation is done by ASIC designers to avoid re-spins. Most FPGA designers will do RTL simulation to identify the functional/RTL codes problem since RLT simulation is faster and user can also see all the internal nodes without seeing bad names signals. For gate level signals, some internal nodes will probably rename or removed during optimization. So you can’t trust the internal node's result . The only signals that are surely survived and trusted are at the external ports.

Typically, FPGA designers will also do Static Timing Analysis via timequest by constraining their design correctly and ensure their design pass multicorner timing analysis. After verifying the RTL simulation and timing analysis, the last thing is to use signaltap II tool to verify the behavior on hardware.