Is RTL Simulation the same as Functional Simulation

Recalling the experience with the integrated simulator of older QII editions the functional simulation missed all timing effects and did just "straight forwared" simulation of logic combination while timing simulation includes the internal device delays according to the chip and the routing.

This does not explain the difference between RTL and functional - I would have expected both to be the same... The difference may be, that RTL is the most "top level" logic implementation while functional at least includes the implementation structure in the chip...

Thus an RTL representation of a 8 signal input "AND" function is just the "AND" function, while the chip implementation requires this 8-AND to be generated of the given LUT by cascading, thus ending up in a lot more logic functions to be evaluated when simulating...

Nevertheless both ways should give (for pure functional) same result as possible timing issues are not taken care of

Just my two cents,

Carlhermann