Is it possible to use ALTLVDS_RX processing single ended signals in Cyclone V GX?

@Corestar:

#1. The LVDS data and clocks are generated by other eight FPGA in other different PCB, and they are sent to the Cyclone V GX FPGA board by cable;

#2. I know I probably can solve this problem by upgrade the hardware design and use a FPGA has more I/Os. But I need to upgrade the hardware design which is time cost and also need to be verified. This type of FPGA are mass used in our products and I don't want to introduce new type of FPGA.

#3. There are eight individual synchronous clocks signals, but I think probably we can use only some of them to collect all of the eight channel data signals.

#4. There are only two LVDS input in one SN65EPT23, the maximum channel to channel skew is 110ps and part to part skew is 400ps.