New Contributor
Contributor@sYimi , I'm a bit confused at this point. Could you clarify what is generating your LVDS data and clocks? It sounds like you have 8 data channels and 1 or 2 clocks.
The simplest solution by far is to simply feed those in as LVDS pairs and use the ALTLVDS_RX core(s) in the normal way. What is preventing you from just doing that? It would only be 10 extra pins and you are using a large package. But if that is the issue, in my opinion, you'd be far better of picking a larger package than adding all these extra chips to the board. I'm afraid I'm having trouble understanding the reason for using level shifting.
And if there are only 1 or 2 clocks, why are you using 8 SN65EPT23 and feeding a data/clock pair into each? Is there a version of the SN65EPT23 that will take 10 inputs?
If you really need to use your current method, the part-to-part skew of the SN65EPT23 is small enough that you may be able to get things working at 200 MHz, but are you sure your clocks are properly aligned? One thing the PLL in the LVDS core allows is to offset the clock so that it is properly centered on the data.
