Is it possible to use ALTLVDS_RX processing single ended signals in Cyclone V GX?

@corestar. Thanks for your great help, we are trying the ALTDDIO IP core now and hope it works. But I am still wondering is it possible to use ALTLVDS_RX to deal with this case. I know, the LVDS signals will be transferred to single ended type inside FPGA and then do deserialization because FPGA logic cell can only process single ended type signals. The only difference is that I use LVDS translator IC translate the signals and then input to FPGA. In fact, we can use one or two synchronous clock to collect all of the eight channel data.

It is described that there is option "Implement Deserializer circuit in logic cell" in page ten of "LVDS Serdes Transmitter/Receiver IP cores User Guide", I guess if we can select this option we probably use single ended IO buffer output to feed in the ALTLVDS_RX IP core. Unfortunately, our firmware engineer told me it is unselectable for Cyclone V GX chip. You can check the attached picture and please help to check why?