Is it possible to use ALTLVDS_RX processing single ended signals in Cyclone V GX?

@sYimi​ , I see what you are saying. That is alot of independent clocks (I'm assuming all the clocks are asynchronous). We use the Cyclone V GX as well, and the ALTLVDS_RX core will require you to have the LVDS clock on a clock input on a compatible bank to the data and will by default use a PLL. So even if it accepted single-ended inputs, you would run out of PLL's. So you will probably have to do clock domain crossing as well.

The next larger CV has 8 PLL's, but that does not leave anything for the rest of the design. However, the ALTLVDS_RX core has an option to use an external PLL. So you could use that on one or more of them and still generate other clocks if needed. It would cost a few dollars more, but save a vast amount of board space and complexity.

It's a shame, in addition to on chip termination, we user the hard IP LVDS to do deserialization. I don't know if it's possible to use those in your case. I'm afraid you need someone more knowledgeable than me to help at this point.