Is it possible to use ALTLVDS_RX processing single ended signals in Cyclone V GX?

Hi Corestar, Appreciated for your help. And here are some extra information:

#1. The FPGA I used is 5CGXFC7D6F27C7N;

#2. I used eight SN65EPT23, one can translate two LVDS signals to LVCMOS. I use eight LVDS data and eight LVDS synchronous clock. So, each SN65EPT23 translate one pair of LVDS data and LVDS clock to LVCMOS data and clock. Clock frequency is 1/10 data frequency; We want to use the synchronous clock to deserialize the data.

#3. There is no internal termination resistor in SN65EPT23, and I use external resistor for them.​