Is it possible to re-enable shared memory caching and manually flush the cache?

We’re allocating shared memory between the FPGA and ARM for several memory buffers by using CL_MEM_ALLOC_HOST_PTR. Our goal is for the FPGA to process and write data to these buffers and then have the ARM perform subsequent operations on the same buffers with as little overhead as possible. Since CPU caching is disabled for shared memory, the ARM access to these buffers is slowed down compared to normal cache enabled memory. To get around this problem we implement memcpy to transfer the data from the shared memory buffers to another array. However, the memcpy itself adds additional processing time. Ideally what we want to do is re-enable the cache for the shared memory and manually flush the cache as needed. Doing so would allow us to avoid expensive memcpy operations, have efficient access to the memory buffers for the additional ARM processing, and maintain cache coherency for the FPGA operations.

The steps we have taken so far are:

1. Re-enable shared memory caching by modifying the aclsoc_drv.ko module.

2. Wrote our own module to access the ARM CPU cache flush utilities in cacheflush.h using the ioctl method.

3. Implemented cache flush before and after the FPGA operations to maintain cache coherency.

The problem is we still seem to have an issue with cache coherency, and we’re seeing stale data. It appears that our custom module is flushing the cache, but the effects do not seem consistent with that. Is there a way to implement what we’re trying to do? Perhaps there is already a solution out there?