Is it possible to implement AES-256 algorithm in Altera cyclone iv E DE2 115 board?

Have a look at "fpga implementation of aes encryption and decryption (http://www.design-reuse.com/articles/13981/fpga-implementation-of-aes-encryption-and-decryption.html)". Having a look at the 'Device utilization summary' I'd suggest you should be able to implement this in the DE2-115's FPGA.