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RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
7 years ago

Is "If elsif else" in this case errant?

I am trying to convert an Open Core from Verilog to VHDL, doing this I converted one to one modules then cheked them till code work by step. After last packet conversion, (transmit logic) I seen a ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago

Its fine, you can send the design using email. One things is that can you check what is your VHDL version that you were using? Are you using VHDL 2008?

The settings is in assignment -> settings -> compiler settings -> VHDL input