Forum Discussion
RRomano001
Contributor
ContributorIs "If elsif else" in this case errant?
I am trying to convert an Open Core from Verilog to VHDL, doing this I converted one to one modules then cheked them till code work by step. After last packet conversion, (transmit logic) I seen a ...
KennyT_altera
Super Contributor
Super ContributorIts fine, you can send the design using email. One things is that can you check what is your VHDL version that you were using? Are you using VHDL 2008?
The settings is in assignment -> settings -> compiler settings -> VHDL input
