Is export/import design partitioning supported when HPS is in the partition?

1. Design your HPS:
   For this example, I used the Quartus Prime Standard 17.1 tools to create a new project. Then I simply copied the GHRD Qsys (converted from Pro to Standard: details in a different post) directory (ghrd_10as066n2/) into my new project directory. I edited the Qsys design by removing all unwanted modules, specifically all modules related to JTAG (ex. 'issp'). These modules seem to result in the generation of sld_hub:auto_hub, which resulted in build problems when this project is imported into an higher-level project.

2. Create a wrapper for the HPS, and build:

3. Within the project created in Step# 1, design a wrapper for the HPS. Here the signals names of the HPS can be mapped to something simplier.

4. 'Add' the qip file, and any other require HDL files, to the project via 'Assignments->Settings->Files'.

5. Edit the qsf to contain set_location_assignment for all of the HPS.

6. Obtain assignments from original GHRD or from the qip.

7. If from the qip, you must convert similar to the following:
   FROM: set_instance_assignment -name HPS_LOCATION PIN_H18 -entity ghrd_10as066n2_altera_arria10_hps_171_g7cowra -to hps_io|border|hps_io_phery_emac0_TX_CLK

[*] Configure for Incremental Compilation

1. 'Assignments->Settings->Compilation Process Setting->Incremental Complication', and check the box for Export Project->'Automatically export design partition after compilation'

2. Use the defaults for the 'Export Design Partition Settings': Netlist to export: 'Top' and 'Post-fit netlist' and 'Post-synthesis netlist' (Note: Post-fit will not be used, but we're generating anyway).

[*] Execute 'Start Compilation' (~8min)

[*] Execute 'Project->Export Design Partition' (<1min)

NOTE: There will be a lot of the following warnings during compilation, but they can be ignored (I think).

Warning (12620): Input port OE of I/O output buffer "hps_i2c1_SDA~output" is not connected, but the atom is driving a bi-directional pin

Warning (12620): Input port OE of I/O output buffer "hps_i2c1_SCL~output" is not connected, but the atom is driving a bi-directional pin

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[*]. Create another project (to emulate OCPI project hierarchy) which will import the wrapped HPS Design Partition:

1. 'Add' the qxp file from Step# 2 to the project's 'Assignments->Settings->Files'.

2. Create a wrapper for the top-level of the project the was create/built in Setup# 1 and 2.

3. Execute 'Start Analysis and Elaboration'.

4. Confirm that sld_hub:auto_hub does not exist in the Project Navigator. If it does exist, work on Step# 1 and 2 to remove it, as it will most likely cause build problems.

[*] Copy/Edit the IO standard info for the HPS pins, from the qip file into the qsf, and change as needed. An example is shown below:

FROM: set_instance_assignment -entity "ghrd_10as066n2_altera_emif_arch_nf_171_tz657la" -library "ghrd_10as066n2_altera_emif_arch_nf_171" -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to "mem_ck[0]"

TO: set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to hps_memory_mem_ck

[*] Import Design Partition for the SoC instance.

1. Right-Mouse-Click on the soc_inst listed in the Project Navigator, and select 'Design Partition->Import Design Partition'.

2. Open the 'Advance Import Settings', and:

3. Uncheck 'Promote assignments to all instances of the imported entity'

4. 'Skip Conflicts...' for 'Logic Lock Regions'

5. 'Skip Conflicts...' for 'Other Assignments'

6. The checkboxes above seem to be settable within the qsf, the the GUI reports the following command/args when the import is actually executed: 'quartus_cdb container -c container --incremental_compilation_import'

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[*] Click OK, then OK again to begin the import process. (<2min)

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[*] Once import is complete, open the 'Assignments->Design Partition Window', and change "Netlist" to "Post-Synthesis".

[*] Execute 'Start Compilation' (~7min)

[*] Execute 'Start Assembler' (<2min). The .rbf is now available.

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