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Altera_Forum
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14 years ago

Is Auto Gated Clock Conversion from non-pin clocks?

It's an old story. FPGA prototyping of ASIC code. Gated clocks are a big headache for timing and bigger headache to manually "fix". Auto Gated Clock Conversion would seem to be the answer but...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thanks. The trick seems to be defining internally generated clock as derived from a pin clock. As least, that's how it worked in my toy design. It is going to take some work to get it into the real design.

create_generated_clock -name {evil_clock} -source [get_ports {clk_in}] -master_clock {clk_in} [get_nets {clk_divider:cdiv|clkOut}]