Forum Discussion
New ContributorIP catalogue different in Platform Designer
Some Intel IP cores may or may not support the Qsys and SOPC Builder design flows and the Native Transceiver Native Phy Intel Cyclone V IP seems to be one of it that does not support the Qsys flow.
You may checkout a similar forum case. There's some broken link which I can't do much about it.
Since you beginning to begin your design with this IP, you may also checkout the Cyclone V Transceiver PHY Basic Design. There are a few design examples that you can refer to:
https://community.intel.com/t5/FPGA-Wiki/Cyclone-V-Transceiver-PHY-Basic-Design-Examples/ta-p/735390
Super ContributorSome Intel IP cores may or may not support the Qsys and SOPC Builder design flows and the Native Transceiver Native Phy Intel Cyclone V IP seems to be one of it that does not support the Qsys flow.
You may checkout a similar forum case. There's some broken link which I can't do much about it.
Since you beginning to begin your design with this IP, you may also checkout the Cyclone V Transceiver PHY Basic Design. There are a few design examples that you can refer to:
https://community.intel.com/t5/FPGA-Wiki/Cyclone-V-Transceiver-PHY-Basic-Design-Examples/ta-p/735390
New ContributorThank you for the quick reaction and insight. I was searching more generally and didn't see the other entry.
That should get me started.
- RichardT_altera
I’m glad that your question has been addressed, I will now transition this thread to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
