Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorI/O Timing constraints when clock is internally generated
Hi. I have a state machine that drives output pins, and also has incoming signals from input pins. The state machine is clocked by the output of a PLL, and the same clock also drives a clock ou...
Altera_ForumHonored Contributor
Honored ContributorTx timing is typical source synchronous but your figures are wrong. You should set max to tSU of phy and min to minus tH of phy.
For Rx your interface is not source synchronous (destination synchronous) and data is opposite clk. You need virtual clock here. The data offset (max,min) = 3~9 tCO of phy + data board delay + clk board delay = say 4 ~ 10 I don't know if you can use output clk if you add generated clk statement.
