I/O Timing constraints when clock is internally generated

Hi Kaz, Mini.

There are data paths in both directions.

For the tx path, the fpga drives clock and data to the PHY. The PHY setup time is 4ns and has a hold time of 2ns. Naturally, this is at the pins. I therefore want to constrain the fpga clock-to out, at the pins, to be minimum 2ns, maximum 16ns.

For the rx path, the FPGA is still clocking the PHY, and the PHY drives rx data to the FPGA with a clock-to out between 3ns and 9ns. I therefore want to constrain the fpga setup time to be no more than 11ns and hold time no more than 3ns. (Again at the pins).

Unfortunately, the PLL is fractional, as the input is 40MHz. (We can't change that, it's used everywhere else).

The 'derive_pll_clocks' entry has been there all the time. See below.

create_clock -period 20 [get_ports aux_eth_ref_clk] // output port, driven by 50MHz PLL output

derive_pll_clocks

set_output_delay -max 16 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_txd*]

set_output_delay -max 16 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_tx_en]

set_output_delay -min 2 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_txd*]

set_output_delay -min 2 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_tx_en]

set_input_delay -max 11 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rxd*]

set_input_delay -max 11 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_dv]

set_input_delay -max 11 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_er]

set_input_delay -min -3 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rxd*]

set_input_delay -min -3 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_dv]

set_input_delay -min -3 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_er]

What else do I need? The tools should know the skew between the clock that drives the state machine, and what appears on the clock pin, right??