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Honored Contributor
Honored ContributorI/O Timing constraints when clock is internally generated
Hi. I have a state machine that drives output pins, and also has incoming signals from input pins. The state machine is clocked by the output of a PLL, and the same clock also drives a clock ou...
Altera_ForumHonored Contributor
Honored ContributorIf I understood, you clock from fpga to get data from phy chip. Hence your interface is not source synchronous as clock is opposite data direction.
Use virtual clock to define data offset. In source synchronous inputs, the tool needs data offset from the clock (min and max). You need to work out this offset expressed relative to virtual clock but derived correctly. You can either derive the offset relative to PLL input clock (if it is base clock) but you might get into trouble if its relation to the 50MHz is fractional. You can derive offset relative to output clock as clock board delay from fpga to phy + phy tCO + data board delay from phy to fpga. enter computed min/max offset relative to virtual clock.
