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Altera_Forum's avatar
Altera_Forum
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15 years ago

io pin assignment

Hi,

I have added an IP core to the sopc builder. generated system no errors. (quartus 8.1) Now trying to connect its output ports which are only 2 lines clock and data to fpga pins. there is also a top level verilog file in quartus, which has io ports defined in it.

Will i have to enter the ipcore's ports in that top level file or can i do it through pin assignment editor? There are other interfaces also defined in the top level file and pin planner generated file is not the same as this top level file.

please help. thanks.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    i'm not quite clear on what's going on. you should have instantiated your SOPC Builder in your top level Verilog file (or in one of the instantiated modules). this instantiation should map the outputs from your SOPC Builder system to outputs of the top level module

    you will still have to assign the I/O locations and specs in Pin Planner/Assignment Editor in addition to "porting" the outputs to the top level of the design