Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Introducing delay in output pin

Hi, I am using Cyclone IV E FPGA in a board. I want to introduce a fixed amount of delay in an output pin. I have instantiated ALTIOBUF component. In the Assignment Editor, I have selected the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The device is EP4CE40F23C6N. The data rate is 480 Mbps. The IO standard is LVDS. I am trying to correct for offsets between 100-500 ps.