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Altera_Forum's avatar
Altera_Forum
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8 years ago

Introducing delay in output pin

Hi, I am using Cyclone IV E FPGA in a board. I want to introduce a fixed amount of delay in an output pin. I have instantiated ALTIOBUF component. In the Assignment Editor, I have selected the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

What device, what 's your data rate(line rate on the IO) and what's your IO standard? How much offset are you trying to correct for?