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Honored Contributor
Honored ContributorIntroducing delay in output pin
Hi, I am using Cyclone IV E FPGA in a board. I want to introduce a fixed amount of delay in an output pin. I have instantiated ALTIOBUF component. In the Assignment Editor, I have selected the...
Altera_ForumHonored Contributor
Honored ContributorHi,
Can you provide more details of your design? Why do you need to implement this delay? By how much you want to delay signal? Why are you using ALTIOBUF? What signal you want to delay? Is it synchronous or asyncronous? Maybe you are entereing invalid values? "Delay from output register to output pin" option has only two valid values 0 and 1. See Cyclone IV datasheet Table 1–42 and Table 1–43.
