Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlname_ela

When I was trying to synthesize following code: process(CLK) begin if rising_edge(CLK) then case find_1st_bit is when first => ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thank you very much for reply. I solved this problem by assigning RAM elements to another additional signal. Thanks a lot again.