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Altera_Forum's avatar
Altera_Forum
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11 years ago

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlname_ela

When I was trying to synthesize following code: process(CLK) begin if rising_edge(CLK) then case find_1st_bit is when first => ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Looking into the code, my guess is that it is the index to RAM3 in the fourth case that might trick the mapper into believing that it could possibly go out of range. What happens if you try to compile with that line looking like this instead:

TRAM(cnt0) <= TRAM(cnt2)(14 downto 0) & RAM3(cnt2)(cnt1);

I understand that it will render a functional bug, I would just compile with this to see if that is what causing Quartus to error out.